The present invention relates generally to the read/write channel in a disk drive. More particularly, the invention is directed to an encoder circuit in the read/write channel for encoding NRZ data input from a host computer to RLL data output to the head/disk assembly of the disk drive.
A typical computer system includes a host computer coupled to other system components by a system bus. The system component typically used for data storage is a disk drive. The operational circuitry for the disk drive would usually include a controller to control drive functions and read/write circuitry to transfer data between the host computer and the disk heads. Host computer data is typically encoded in a nonreturn to zero (NRZ) format, which is a method of coding data in which the signal representing binary digits alternates between a positive and zero voltage when there is a change in successive bits, either from a high (1) to a low (0), or vice versa. Disk data, on the other hand, is stored according to a run length limited (RLL) format, which is another method of coding data. RLL coding avoids the possibility of a data stream including a lengthy sequence of consecutive high or low signal values. RLL coding must be used in the disk drive because the phase-locked loop and automatic gain control circuitry used in storing data on and reading data from the disk require alternative high and low signals in order to provide accurate performance. For example, one possible RLL encoding scheme is RLL (1,7), which means that for every seven low signal values, there must be at least one high signal value.
Each data stream, NRZ data and RLL data, has its own clock for transferring data through the system, the NRZ clock and RLL clock, respectively. The NRZ data from the host is encoded into RLL data for the disk heads in the read/write channel encoder circuitry. Both the NRZ clock and RLL clock must remain properly synchronized in relation to each other in order to ensure that data is encoded accurately. If the encoding operates asynchronously, the encoded RLL output will not accurately reflect the NRZ data input. One possible reason for asychronous operation is a temperature-induced clock drift, which would cause a triggering clock edge outside of its associated data window. Current encoder circuits use a signal operating at twice the frequency of the RLL clock to lock the RLL data window to the NRZ data window. This approach is effective at lower frequencies of the RLL clock, but breaks down as the RLL clock frequency reaches its upper limit, where the faster RLL clock is not available due to manufacturing process limitations.
Thus, it would be desirable to have an encoder circuit that can synchronize the NRZ clock and RLL clock even at high frequencies of the RLL clock.